Cache Simulator
Visualize cache behavior with interactive memory access patterns
Play to auto-run • Step for single access • Generate to reset
🎮 Simulation Controls
📋 Cache Lines
| # | Valid | Tag | Off 0 | Off 1 | Off 2 | Off 3 | LRU |
|---|
📈 Hit vs Miss
💽 RAM Overview
Hit
Miss
Prefetch
📜 Access Log
💡 How to Use This Simulator
- Configure memory settings in the sidebar (RAM size, block size, cache lines, associativity).
- Select an access pattern to simulate different memory access behaviors.
- Click Generate to create a new access sequence, or Play to auto-run.
- Use Step to advance one memory access at a time.
- Watch the cache table, RAM view, and chart update in real-time.
Access Patterns Explained
- Sequential: Accesses addresses 0, 1, 2, ... like a simple loop.
- Reverse: Accesses N-1, N-2, ... iterating backward.
- Strided: Accesses 0, S, 2S, ... stepping by stride value.
- Random: Shuffled addresses, simulating pointer-chasing.
Understanding Cache Behavior
- Cache Hit
- Data found in cache - fast access (10 ns).
- Cache Miss
- Data not in cache - must fetch from RAM (100 ns).
- Prefetch
- Speculatively load next blocks to reduce future misses.
- LRU (Least Recently Used)
- Eviction policy - removes oldest unused cache line when full.